Endurances of memory cells of non-volatile memories, for example, flash memories, are limited. Once a memory cell endures a certain number of writing and erasing cycles, the memory cell becomes worn out, and data stored in the memory cell will lose.
FIG. 1 (prior art) is a schematic diagram illustrating the stage transition of a memory unit (MU1) in a memory device. A memory device 10 includes a control circuit 11 and a memory array 13, and the memory array 13 further includes multiple memory units (MUs). For the sake of illustration, only two of the memory units are shown. Usually, the endurance of the memory unit can be represented as four different stages, a fresh stage (stage I), a stable stage (stage II), a risky stage (stage III), and a failure stage (stage IV). The four stages of memory unit MU1 are briefly described below.
The upper left corner of FIG. 1 shows that both the memory unit MU1 and memory unit MU2 are at their fresh stage at the beginning. That is, the memory array 13 is newly erased and both the memory unit MU1 and memory unit MU2 are empty.
At the upper right corner of FIG. 1, the grids of the memory unit MU1 represent that the memory unit MU1 is at the stable stage. When a memory unit is at the stable stage, the data stored in the memory unit can be safely retrieved.
At the lower right corner of FIG. 1, the diagonal stripes of the memory unit MU1 represent that the memory unit MU1 is at the risky stage. When a memory unit is at the risky stage, the data stored in the memory unit can still be retrieved, but more consequential accesses to the memory unit may cause failure.
At lower left corner of FIG. 1, the saltires of the memory unit MU1 represent that the memory unit MU1 is at the failure stage. When a memory unit is at the failure stage, data retention errors occur and the data previously stored in the memory unit are no longer available.
Therefore, once the memory unit is at the risky stage, consequential access to the memory unit should be avoided. Alternatively speaking, it is important to identify whether the memory unit is about to be at the failure stage in advance.